Rangharajan Venkatesan. Yang Hu. Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer. Yakun Sophia Shao is with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720 USA. Rangharajan Venkatesan NVIDIA Santa Clara, CA, USA rangharajanv@nvidia.com Ben Keller NVIDIA Santa Clara, CA, USA benk@nvidia.com Brucek Khailany NVIDIA Austin, TX, USA bkhailany@nvidia.com AbstractHigh-level synthesis (HLS) has recently been used to improve design productivity for many units in today's complex SoCs. Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, and Brian Zimmer, "A modular digital VLSI flow for high-productivity SoC design," in Proceedings of . Deep Learning Hardware Machine Learning for EDA Agile Hardware Design Methodology Spin Memories. 0 followers Featured Co-authors. IEEE, 2017. Find Rangharajan Venkatesan's accurate email address and contact/phone number in Adapt.io. Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, and Brian Zimmer, "A modular digital VLSI flow for high-productivity SoC design," in Proceedings of . Nathaniel Pinckney. Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel Emer March 2019 In ISPASS Timeloop: A Systematic Approach to DNN Accelerator Evaluation GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks . Title. Huazhong University of Science and Technology. Senior Research Scientist, NVIDIA. He received the B.Tech. 27-40. Biblio data only below the dashed line. Priyanka Raina. ISCA'17. IEEE Journal of Solid-State Circuits (JSSC), February 2021. Crafting an effective statement of purpose March 16, 2021; SOP Sample From Khorana Alum February 19, 2021; The Covid-19 Research: How India Responds? Abstract. SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. Rangharajan Venkatesan: NVIDIA: Ravi Rajwar: Google: Ravishankar Iyer: Intel: Rene Mueller: Huawei Zurich Research Center, Switzerland: Resit Sendag: University of Rhode Island: Ronald Dreslinski: University of Michigan: Rui Hou: Institute of Information Engineering, Chinese Academy of Sciences: Rujia Wang: Illinois Institute of Technology . HP Enterprise Gen-Z Chipset. Full text data coming soon. The IEEE Circuits and Systems Society is the leading organization that promotes the advancement of the theory, analysis, computer-aided design and practical implementation of circuits, and the application of circuit theoretic techniques to systems and signal processing. Past JSSC Best Paper Award Winners Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, more Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 > 356 - 361 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE) Institute of Information Engineering, Chinese Academy of Sciences. Search within Rangharajan Venkatesan's work. Joel S. Emer Thomas Gray. His research interests include machine learning accelerators, low-power VLSI design, and SoC design methodologies. This hardware-software synergy leads to an elegant exten-sion of current accelerator architectures for implementing per-vector scaling with low overhead. ACM/IEEE Design Automation Conference (DAC), June 2018 . Rangharajan Venkatesan. Nan Jiang Ben Keller. University of Florida. Rangharajan VENKATESAN has filed for patents to protect the following inventions. Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Stephen W. Keckler, and William J. Dally. 2. The field of interest covered includes: HLS tools Sponsored by IEEE and SSCS, the International Solid-State Circuits Conference - ISSCC - is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. People: Angshuman Parashar, Priyanka Raina, Sophia Shao, Rangharajan Venkatesan, Yu-Hsin Chen, Brucek Khailany, Stephen W. Keckler, Joel Emer. Timeloop: A Systematic Approach to DNN Accelerator Evaluation. Two different spintronic memory technologies Domain Wall Memory (DWM) and STT-MRAM . TCAS-II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Rangharajan Venkatesan In Partial Fulllment of the Requirements for the Degree of Doctor of Philosophy December 2014 Purdue University West Lafayette, Indiana. Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Stephen W. Keckler, and William J. Dally. The major contribu-tions of our work are as follows: We propose VS-Quant, a novel per-vector scaled quantiza- He is currently pursuing the Ph.D. degree with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA. Jour- Domain-Specific Many-core Computing using Spin-based Memorymore. Figure 1 illustrates the three-level hierarchy of the Simba architecture: package, chiplet, and PE. In ISPASS. IEEE Journal of Solid-State Circuits 55 (4), 920-932, 2020. B Keller, M Fojtik, B Khailany. Yakun Sophia Shao. "Scnn: An accelerator for compressed-sparse convolutional neural networks." In 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), pp. 3.3. Presenter Name: Institution: Title: Kaushik Roy. The 36-chiplet Simba system is functional over a slightly narrower voltage range, from 0.52 to 1.1 V, achieving 0.16 pJ/op at 0.52 V and 484 MHz; at 1.1 V, the 36-chiplet system achieves a 1.8 GHz PE frequency and 128 TOPS. Rangharajan has 7 jobs listed on their profile. Agendas April Mini-Workshop Monday, April 27. Huawei Zurich Research Center, Switzerland. Verified email at nvidia.com - Homepage. Authors: Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Ming-Yu Liu, Brucek Khailany, Bill Dally, Anima Anandkumar. Nima Honarmand. Rangharajan Venkatesan. Crafting an effective statement of purpose March 16, 2021; SOP Sample From Khorana Alum February 19, 2021; The Covid-19 Research: How India Responds? Rangharajan Venkatesan. Recent News. This involves three chiplets that are built on the same reticle, but are then combined in different . Rangharajan Venkatesan is a Senior Research Scientist with NVIDIA. Yu Hua. 1) It explores the use of spintronic memories in the design of a domain-specific processor for an emerging class of data-intensive applications, namely recognition, mining and synthesis (RMS). Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Stephen W. Keckler, and William J. Dally. Steve Dai 4 publications . Authors: Steve Dai, Rangharajan Venkatesan, Haoxing Ren, Brian Zimmer, William J. Dally, Brucek Khailany. ACM is meeting this challenge, continuing to work to improve the automated merges by tweaking the weighting of the evidence in light of experience. MAGNet: A Modular Accelerator Generator for Neural Networks Rangharajan Venkatesan, yYakun Sophia Shao, Miaorong Wang,zJason Clemons, Steve Dai, yMatthew Fojtik, Ben Keller, yAlicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang,yBrian Zimmer,y William J. Dally, yJoel Emer,yzStephen W. Keckler, Brucek Khailanyy NVIDIAy Massachusetts Institute of Technologyz Stanford University Ming-Yu Liu 48 publications . May 2014 Session: Rangharajan Venkatesan, Purdue University July 2014 Session: Shankar Ganesh Ramasubramanian, Purdue University November 2014 Session: Mihir Pendharkar, University of California - Santa Barbara. PRIMAL: Power Inference using Machine Learning Yuan Zhou, Haoxing Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang. arXiv preprint arXiv:2103.09301. mans;Venkatesan et al.,2019;NVIDIA Corporation,2020). Anand Raghunathan. 6 | COMMUNICATIONS OF THE ACM 107 Simba: Scaling Deep-Learning Inference with Chiplet-Based Architecture By Yakun Sophia Shao, Jason Cemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Figure 1 (a) shows a Simba package consisting of a 6x6 array of Simba chiplets connected via a mesh interconnect. Fax: 205-921-5595 2131 Military Street S Hamilton, AL 35570 View Location The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts. It is shown that the holistic device-circuit-architecture co-design enables all the levels in the cache hierarchy to be realized using DWM and benefit from its improved density, and proposes TapeCache, a DWM-based cache design that employs device, circuit, and architectural techniques to address these challenges. 205-921-5556. Anima Anandkumar 121 publications . 2018 A Modular Digital VLSI Flow for High-Productivity SoC Design Brucek Khailany, Matthew Fojtik, Alicia Klinefelter, Evgeni Krimer, Michael Pellauer, Nathaniel Pinck- Differential evolution-a simple and efcient heuristic for global optimization over continuous spaces. Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. 2017. Download PDF Abstract: Representing deep neural networks (DNNs) in low-precision is a promising approach to enable efficient acceleration and memory reduction. 2021. Chinese Academy of Sciences, Institute of Computing Technology. Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel Emer International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2019. There was strong difference of opinion between the petitioner/husband and the respondent/wife during their Marital . Huawei Technologies. degree in electronics and communication engineering from Indian Institute of Technology, Roorkee, India, in 2009. Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina . JUNE 2021 | VOL. October 3, 2020; Sign Up to Receive Our Newsletter . Rangharajan Venkatesan is this you? newest | popular; Activity Feed; Likes; 0 research 03/19/2021. Spin-based devices have shown great potential in enabling high-density, energy-efficient memory and are therefore, considered highly promising for the design of future computing platforms. Rangharajan Venkatesan: NVIDIA: Ravi Rajwar: Google: Ravishankar Iyer: Intel: Rene Mueller: Huawei Zurich Research Center, Switzerland: Resit Sendag: University of Rhode Island: Ronald Dreslinski: University of Michigan: Rui Hou: Institute of Information Engineering, Chinese Academy of Sciences: Rujia Wang: Illinois Institute of Technology . 64 | NO. See the complete profile on LinkedIn and discover . 2017. Rangharajan Venkatesan is a Senior Research Scientist in the ASIC & VLSI Research group in NVIDIA. Previous methods that train DNNs in low-precision typically keep a . Senior Research Scientist, NVIDIA - Cited by 2,296 - Deep Learning Hardware - Machine Learning for EDA - Agile Hardware Design Methodology - Spin Memories Skip slideshow. Search Search. How to say Rangharajan Venkatesan in English? In Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA '17 . (7/31) The electronic proceedings is also accessible online when you login as user "ISLPED2012" with the Wi-Fi passport as handed out at the symposium. Rangharajan Venkatesan: NVIDIA: Ravi Soundararajan: VMware: Reetuparna Das: University of Michigan: Resit Sendag: University of Rhode Island: Reza Hojabr: Simon Fraser University: Robert Bell: Samsung: Ronald Dreslinski: University of Michigan: Ruby Lee: Princeton: Rui Hou: Institute of Information Engineering, Chinese Academy of Sciences . Anand Raghunathan 18 publications . ii ACKNOWLEDGMENTS First and foremost, I would like to express my sincere gratitude to my advisor, SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks Angshuman Parashar Minsoo Rhu Anurag Mukkara Antonio Puglielli Rangharajan Venkatesan Brucek Khailany Joel Emer Stephen W. Keckler William J. Dally NVIDIA Massachusetts Institute of Technology UC-Berkeley Stanford University aparashar@nvidia.com . Yu Hua. [13] Rainer Storn and Kenneth Price. Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen G Tell, Yanqing Zhang, William J Dally, Joel S Emer, C Thomas Gray, Stephen W Keckler, Brucek Khailany Stephen G. Tell. Most frequent co-Author . Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fo-jtik, Ben Keller, Alicia Klinelter, Nathaniel Pinckney, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany International Conference on Computer Aided Design (ICCAD), November 2019 (7/27) The final program has been updated.. Scnn: An accelerator for compressed-sparse convolutional neural networks. Jacob R Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, and Anand Raghunathan. Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally: ACM Transactions on Computer Systems, September 2015: Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems, 1-8, 2015. Rangharajan Venkatesan of NVIDIA presented their research project using network-on-chip (NoC) and network-on-package (NoP) chiplet integration strategy. Quantization maps floating-point weights and activations in a . Huawei Zurich Research Center. Rangharajan Venkatesan: NVIDIA: Ravi Soundararajan: VMware: Reetuparna Das: University of Michigan: Resit Sendag: University of Rhode Island: Reza Hojabr: Simon Fraser University: Robert Bell: Samsung: Ronald Dreslinski: University of Michigan: Ruby Lee: Princeton: Rui Hou: Institute of Information Engineering, Chinese Academy of Sciences . Home Rangharajan Venkatesan. Brian Zimmer, Rangharajan Venkatesan, Ben Keller, Yanqing Zhang, and William J. Dally are with NVIDIA Corporation, Santa Clara, CA 94305 USA (e-mail: bzimmer@nvidia.com). Alicia Klinefelter. Rangharajan Venkatesan. William J. Dally 17 publications . Scaling Equations for the Accurate Prediction of CMOS Device Performance from . Timeloop uses a concise and unified representation of the key . Google Scholar; Aaron Stillmaker and Bevan Baas. , Stephen W. Keckler, Zhengya Zhang. SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. Sanchari Sen 4 publications . Ali Javadi-Abhari. Date Recorded: Party: Role: Document Type: Document No. Minsoo Rhu . Rangharajan Venkatesan's 20 research works with 1,158 citations and 2,239 reads, including: Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update 27: This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO). His research interests include variation-tolerant design . He has served as a member of the technical program committees of several leading IEEE conferences including International Solid-State Circuits Conference . Amrit Nagarajan 1 publication. October 3, 2020; Sign Up to Receive Our Newsletter . 28: 2020: A pausible bisynchronous FIFO for GALS systems. Some photos can be found in the gallery link. PDF Code WINStep Forward Promoting Science and Technology Between India and the U.S Sort. A 6T SRAM design at a sub-10-nm node calls for carefully designed transistors so that new leakage mechanisms, such as direct source-to-drain . Independent Consultant. Yanqing Zhang. Recent News. STT-MRAM has attracted great interest for use as on-chip memory due to its high density, near-zero leakage and high endurance. by Rangharajan Venkatesan and Charles Augustine. Bibliometrics: In 1926, Alfred Lotka formulated his power law (known as Lotka's Law) describing the frequency of publication by authors in a given field. However, its overall energy efficiency is limited by the energy requirements of spin-transfer torque switching during writes and reliable single-ended sensing during reads. William J. Dally. Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik,Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina . B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, . WINStep Forward Promoting Science and Technology Between India and the U.S Rangharajan Venkatesan vs Anjali Srikanth on 27 January, 2021. Rene Mueller. Awards Two best-paper awards and four design-contest awards were given out at the banquet on July 31. Each Simba chiplet, as shown in Figure 1 (b), contains an array of PEs, a global PE, a NoP router, and a controller, all connected . Rangharajan Venkatesan received the B.Tech. Rui Hou. Tensorloop is an infrastructure for evaluating and exploring the architecture design space of deep neural network (DNN) accelerators. Stephen W. Keckler Brucek Khailany . Aritra Dhar. Domain wall memory (DWM) is a recently developed spin-based memory technology in . (8/1) We have had a very successful event! Rangharajan Venkatesan. Xing Hu. Venkatesan, Rangharajan has not filed any forms with the United States Securities and Exchange Commission. Patrick Knebel of HP Enterprise presented their Gen-Z chipset. Rangharajan Venkatesan 5 publications . Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes A. ARUN GOUD, RANGHARAJAN VENKATESAN, ANAND RAGHUNATHAN, and KAUSHIK ROY, Purdue University, West Lafayette, Indiana Extending double-gate FinFET scaling to sub-10nm technology regime requires device-engineering techniques for countering the rise of direct source to drain tunneling (DSDT . Jason Clemons. Invention Title: 2/3/2022: Nvidia Corporation: Assignee: Application Publication: 17530852 20220076110: Efficient Neural Network Accelerator Dataflows no code implementations 23 May 2017 Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel Emer, Stephen W. Keckler, William J. Dally Convolutional Neural Networks (CNNs) have emerged as a fundamental technology for machine learning. Rangharajan Venkatesan. degree in Electronics and Communication Engineering from the Indian Institute of Technology, Roorkee in 2009 and the Ph.D. degree in Electrical and Computer Engineering from Purdue University in August 2014. SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks Angshuman Parashar Minsoo Rhu Anurag Mukkara Antonio Puglielli Rangharajan Venkatesan Brucek Khailany Joel Emer Stephen W. Keckler William J. Dally NVIDIA Massachusetts Institute of Technology UC-Berkeley Stanford University . dac 2019: 39 [doi] A 0.11 pJ/Op, .32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason .